485总线在电能表使用中的常见问题及分析--
1 在电能表中的应用
由于历史的原因，我国在制定DL／T614－1997《电子式多功能电能表》及 DL／T645－1997《电子式多功能电能表通讯协议》时将RS－485标准串行通讯接口作为电表的通讯接口，并详细地定义了物理层、链路层、应用层， 结束了以前电表厂家规约各不兼容、互相不能抄的尴尬局面。各电表厂家遵循相同的协议标准对电表进行读写操作，简化了电表抄表应用及维护的工作量。使得国内 的智能电表基本上可以做到互联互通。但是目前国内的485抄表还存在一些问题，主要是通信成功率低、不能做到即连即通、易损坏等。
2 物理层、链 路层及数据传输
2．1 物理层
A）共模输入电压：－7V～＋12V。
B）差模输入电压：大于0．2V。
C） 三态方式输出。
D）半双工通信方式。
E）驱动能力不小于32个同类接口。
F）总线是无源的，由费率装置 或数据终端提供电源。
G）逻辑“1”以A、B两线间的电压差为＋（2～6）V表示；逻辑“0”以两线间的电压差为－（2～6）V表示。
2．2 链路层及数据传输
通讯链路的建立与解除由主站发出的信息帧来控制，帧的组成如表：
由上表可知，帧由起始符、地址域、 控制码、数据长度、数据域、校验码及结束符等7个域组成，每部分由若干字节组成。
DL／T645－1997规定，在发送帧信息之前，先发 送1～4个字节FEH，其目的是预先拉高控制总线，以唤醒接收方，保障帧信息的顺利接收。
DL／T645－1997规定了主?从结构的半 双工通讯方式。每次通讯都是由主站向从站发出请求命令帧开始，从站根据要求作出响应。收到命令帧后的响应延时称作帧间延时 Td：20ms≤Td≤500ms。字节之间停顿时间称作字节间延时Tb：Tb≤500ms。如图1所示：
3 RS485在电表通讯中 的常见问题及解决方案
3．1 收发时序不匹配
现象1：485通讯不成功，用逻辑分析仪查看，发送的码字正确，电能表返回码字也符 合规约。再细看，主站发送的码字的最后一位同电能表应答的数据帧的第一位之间几乎没有停顿。
分析：由于485总线是一个半双工的通讯方 式，收和发不能同时进行，从发送完成到变为接收状态，无论是软件的处理抑或是硬件的切换都需要一定的延时，因此DL／T645规定帧间延时 Td：20ms≤Td≤500ms，主要是给发送方一个由发转为收的时间，保证接收方返回的数据能完整的被接收。而有些电能表，尤其是一些早期的多功能表 对此考虑不够，在接收到主站的请求命令帧后，未进行帧响应延时，就立刻发送应答帧，而此时主站还处于发送状态，等主站返回到接收状态时，电能表前面的码字 已发送完，主站接收到的应答数据帧不完整引起通信失败。
现象2：当主站对某块表连续抄几帧数据时，第一帧通讯成功，第二帧开始电表不回应 答帧。
分析：同样的道理，电表的485由发转为收也需要延时，而有的主站软件编程时，没有考虑，接收完一帧数据后没有延时或延时不够就又 开始抄下一帧，而此时电表还没有回到接收状态，通讯失败。在这里我们建议通信双方在编程时都必须严格遵守DL／T645所规定的帧间延时，并留有余量，具 体应用时可取一个中间值，如100ms。
3．2 判断帧起始符出错
对于电能表485总线来讲，它是一种数字异步通信方式。异步通 信不象同步通信，其没有专门的同步信号进行同步，接收方无法准确判知哪一个字节是一帧数据通信的开始，因此DL／T645中规定68H作为帧起始符（帧同 步码），代表一帧数据的开始。有些主站和电能表在软件编程时考虑得比较理想，接收数据时未按照DL／T645中规定68H来判定数据帧的开始，而是呆板的 以接收到的第一个字符作为帧起始标志；如果电表在此帧数据之前发了几个FEH，其接收到的数据将会出现同步错误。另外，如总线上平时有干扰信号存在，导致 485芯片不停地收到诸如FCH、DEH这样杂乱数据；当总线上有正常信号产生时，由于干扰信号比较小的原因，其对通信并无太大的影响，但对接收方来讲， 其接收正确数据帧前会混有若干个字节的杂乱数据，由于同步处理不当，通讯也会失败。通常的做法是每接收一个字节都要判是否是68H，若不是则丢掉该字节， 然后继续往下判，直到收到68H才启动一帧数据的接收。
3．3 帧奇偶校验位／帧结束符不合理
目前看来，由于这个原因引起485 通信不成功占有很大的比例。我们知道，在485通信时，对于接收到的数据一般都会按收、发双方事先约定的奇偶校验方式进行数据检错，并将错误的数据帧剔 除，等待发送方重发。这种ARQ的通信方式本身是无可厚非的，但是有的软件人员在编程时考虑问题不够全面，在判断一帧结束处理时，没有根据所收数据帧的长 度和结束符“16H”及时地将数据接收任务结束，而是依据多长时间内收不到新的一个字节数据来认为一帧已收完。这种处理方法在下面这种情况下就会导致通信 失败。
众所周知，RS485芯片的接收灵敏度为±200mV，即当电压UA?UB≥200mV时，输出逻辑 “1”；UA?UB≤－200mV时，输出逻辑“0”。当－200mV＜UA?UB＜200mV时，输出不确定。这样一来，当总线上所有的485芯片均处 于接收状态时，总线处于高阻状态，此时A、B间的压差为0V，芯片输出处于不定状态，可能输出“1”，也可能输出“0”，而且状态会随着时间而变化。如果 输出为“0”，在某些时候则会导致通信失败。我们知道，电能表在发送完应答帧后，一般会马上从发送状态转换到接收状态。正常情况应该是：主站的485芯片 收完最后一个字节的停止位后继续保持为“1”（波形见图2），而有的485芯片则可能跳变保持为“0”（波形见图3），UART（通用异步收发器）则认为 又收到一个字节00H，且很有可能校验和是错的，这样接收软件可能会判断到一个字节校验位出错，而将前面接收完全正确的一帧丢掉，造成通信失败。
FROM: http://www.any17.com/newscenter/new/gongl/2006090308084321.html
2010年2月28日星期日
2010年1月6日星期三
VGA analogue display connector
ePanorama.net - VGA analogue display connector: "VGA analogue display connector
Nearly all modern PC graphics cards use the same 15 pin conenctor that the original IBM VGA card used. The connector is not very suitable for high resolution graphics because it does not have a well defined impedance characteristics like BNC connectors. 15 pin VGA connector is still commonly used because it is so popular that it is hard to sell product without it.
Pin numbering in female connector
VGA connector picture
Pinout
1 Red out *
2 Green out *
3 Blue out *
4 Monitor ID 2 in
5 Ground
6 Red return
7 Green return
8 Blue return
9 no pin
10 Sync return
11 Monitor ID 0 in
12 Monitor ID 1 in
13 Horizonal Sync out
14 Vertical Sync out
15 reserved (monitor ID 3)
Signals marked with * are analogue 0.7V p-p positive signals to 75 ohm load. All other signals are TTL level signals.
Here is an ASCII pinout diagram for those who prefer it:
6
1 Red (Analog) 6 Red Return 11 (ID0) GND (Color) 11. . . 1
2 Green (Analog) 7 Green Return 12 (ID1) NC (Color) . . .
3 Blue (Analog) 8 Blue Retuen 13 Horzontal Sync . . .
4 Reserved 9 No Connect 14 Vertical Sync . . .
5 Ground 10 Ground 15 No Connect . . .
15 10 5
Monitor ID detection pin assignments
4 11 12
ID2 ID0 ID1
n/c n/c n/c no monitor
n/c n/c GND Mono monitor which does not sopport 1024x768
n/c GND n/c Color monitor which does not support 1024x768
GND GND n/c Color monitor which supports 1024x768
GND menas connected to ground
n/c means that the pin has not bee connected anywhere
This monitor type detection is becoming more and more obsolete nowadays, because more and mode intelligence is integrated to the monitor. New plug-and-play monitors communicate with the computer according to VESA DDC standard.
VESA DDC
VESA Display Data Channel is a method for integrating digital interface to VGA conenctor to be able the monitor and grapahics card to communicate. There are two different levels of DDC: DDC1 and DDC2.
DDC1
DDC1 allows the monitor to tell it's parapeters to the computer. The following VGA card connector pins had to be changed to allow DDC1 fuctions:
pin new function
9 Optional +5V output from graphics card
12 Data from display
14 Standard vertical sync signal which works also as data clock
15 Monitor ID3
When grpahics card detects data on data-line it starts to read the data coming from the monitor syncronous to vertical sync pulse. Vertical sync pulse frequency can be increased up to 25 KHz for the time of the data transfer if a DDC1 compliant monitor is found (be sure not to send those high frequencies to non DDC1 monitors!).
DDC2
DDC2 allows bidirectional communication: monitor can tell it's parameters and computer can adjust monitor settings. The bidirectional data bus is a syncronous data bus similar to Access Bus and is based on I2C technology. Tho following pins had to be changed to to enable DDC2 to work:
pin new function
9 Optional +5V output from graphics card
12 Bidirectional data line (SDA)
15 Data clock (SLC)
The signals in the data bus are standard I2C signals. The computer provides 15 kohm pullup for the SDA and SLC lines. Monitor must provide 47 kohm pull-up on SCLK line.
NOTE: If the optional +5V power output pin is used, a special DDC/VGA connector must be used to to provide proper sequencing. The +5V output voltage must be withing +/-5% range and tha card must be able to supply at least 300 mA current (maximum 1A).
VESA DPMS power saving
VESA has defined a standard method for computer to tell monitor when to go to power saving mode. This power saving mode is controlled by changing the sync signals according the table below:
NORMAL STANDBY SUSPENDED OFF
H-sync On Off On Off
V-sync On On Off Off
Power level 100% 80% <30W <8W"
Nearly all modern PC graphics cards use the same 15 pin conenctor that the original IBM VGA card used. The connector is not very suitable for high resolution graphics because it does not have a well defined impedance characteristics like BNC connectors. 15 pin VGA connector is still commonly used because it is so popular that it is hard to sell product without it.
Pin numbering in female connector
VGA connector picture
Pinout
1 Red out *
2 Green out *
3 Blue out *
4 Monitor ID 2 in
5 Ground
6 Red return
7 Green return
8 Blue return
9 no pin
10 Sync return
11 Monitor ID 0 in
12 Monitor ID 1 in
13 Horizonal Sync out
14 Vertical Sync out
15 reserved (monitor ID 3)
Signals marked with * are analogue 0.7V p-p positive signals to 75 ohm load. All other signals are TTL level signals.
Here is an ASCII pinout diagram for those who prefer it:
6
1 Red (Analog) 6 Red Return 11 (ID0) GND (Color) 11. . . 1
2 Green (Analog) 7 Green Return 12 (ID1) NC (Color) . . .
3 Blue (Analog) 8 Blue Retuen 13 Horzontal Sync . . .
4 Reserved 9 No Connect 14 Vertical Sync . . .
5 Ground 10 Ground 15 No Connect . . .
15 10 5
Monitor ID detection pin assignments
4 11 12
ID2 ID0 ID1
n/c n/c n/c no monitor
n/c n/c GND Mono monitor which does not sopport 1024x768
n/c GND n/c Color monitor which does not support 1024x768
GND GND n/c Color monitor which supports 1024x768
GND menas connected to ground
n/c means that the pin has not bee connected anywhere
This monitor type detection is becoming more and more obsolete nowadays, because more and mode intelligence is integrated to the monitor. New plug-and-play monitors communicate with the computer according to VESA DDC standard.
VESA DDC
VESA Display Data Channel is a method for integrating digital interface to VGA conenctor to be able the monitor and grapahics card to communicate. There are two different levels of DDC: DDC1 and DDC2.
DDC1
DDC1 allows the monitor to tell it's parapeters to the computer. The following VGA card connector pins had to be changed to allow DDC1 fuctions:
pin new function
9 Optional +5V output from graphics card
12 Data from display
14 Standard vertical sync signal which works also as data clock
15 Monitor ID3
When grpahics card detects data on data-line it starts to read the data coming from the monitor syncronous to vertical sync pulse. Vertical sync pulse frequency can be increased up to 25 KHz for the time of the data transfer if a DDC1 compliant monitor is found (be sure not to send those high frequencies to non DDC1 monitors!).
DDC2
DDC2 allows bidirectional communication: monitor can tell it's parameters and computer can adjust monitor settings. The bidirectional data bus is a syncronous data bus similar to Access Bus and is based on I2C technology. Tho following pins had to be changed to to enable DDC2 to work:
pin new function
9 Optional +5V output from graphics card
12 Bidirectional data line (SDA)
15 Data clock (SLC)
The signals in the data bus are standard I2C signals. The computer provides 15 kohm pullup for the SDA and SLC lines. Monitor must provide 47 kohm pull-up on SCLK line.
NOTE: If the optional +5V power output pin is used, a special DDC/VGA connector must be used to to provide proper sequencing. The +5V output voltage must be withing +/-5% range and tha card must be able to supply at least 300 mA current (maximum 1A).
VESA DPMS power saving
VESA has defined a standard method for computer to tell monitor when to go to power saving mode. This power saving mode is controlled by changing the sync signals according the table below:
NORMAL STANDBY SUSPENDED OFF
H-sync On Off On Off
V-sync On On Off Off
Power level 100% 80% <30W <8W"
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